Field effect transistors are comprised of a pair of diffusion regions, referred to as a source and a drain, spaced apart within a semiconductive substrate. Such include a gate provided adjacent the separation region and between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate area adjacent the gate and between the diffusion regions is referred to as the channel. The semiconductive substrate typically comprises a bulk monocrystalline silicon substrate having a light conductivity dopant impurity concentration. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material over an underlying insulating layer. Such are commonly referred to as semiconductor-on-insulator (SOI) constructions.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths greater than 2 microns) to short-channel devices (i.e., channel lengths less than 2 microns).
As field effect transistor channel lengths (i.e., gate widths) became smaller than about 3 microns, so-called short channel effects began to become increasingly significant. As a result, device design and consequently process technology had to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example, as device dimensions are reduced and the supply voltage remains constant, the lateral electric field generated within the substrate increases. If the field becomes strong enough, it can give rise to so-called hot-carrier effects. This becomes a significant problem with channel lengths smaller than 1.5 microns. Hot-carrier effects cause unacceptable performance degradation in n-type transistor devices built with conventional drain structures if their channel lengths are less than 2 microns.
A preferred method of overcoming this problem is to provide lightly doped drain (LDD) regions within the substrate relative to the channel region in advance of the source and drain regions. The LDD regions are provided to be lighter conductively doped (i.e., less concentration) than the source and drain regions. This facilitates sharing of the voltage drop by the drain in the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD n-type transistors. The LDD regions absorb some of the voltage drop potential into the drain, thus effectively eliminating hot carrier effects. As a result, the stability of the device is increased.
However, further shrinking of the gate width (i.e., shorter channel length) makes the LDD region of a conventional transistor less effective. For example, shorter channel lengths require the LDD length to be reduced to ensure sufficient semiconductive material between the diffusion regions to prevent conductance when the gate voltage is off. One way of attending to such problems is to displace the predominant portion of the source and drain regions outwardly away from the substrate by elevating them. For example, a thin (e.g., 200-nm) epitaxial layer of monocrystalline silicon can be selectively grown from an exposed monocrystalline source and drain substrate areas within an epi reactor, and provided with sufficiently high conductivity doping to effectively provide source and drain regions. The lighter doped LDD regions can be provided within the substrate immediately below the elevated source and drain. Thus, a channel of sufficient length is effectively provided despite the smaller width gate.
One preferred prior art method for providing elevated sources and drains is to first provide a contact opening within an insulating dielectric layer immediately adjacent a word line over the desired source and drain regions. The word line is encapsulated in an insulative nitride material, with the insulating dielectric layer through which the contact openings are provided comprising borophosphosilicate (BPSG). Ideally, etch chemistry for the contact etching through the BPSG layer is selected to be highly selective to the nitride, thereby preventing word line etch rendering the process substantially self-aligning to the word line. One drawback, however, is an inherent difficulty in etching BPSG selectively relative to a nitride encapsulated word line.
Accordingly, it would be desirable to overcome certain of these drawbacks of the prior art. The invention arose primarily out of concerns associated with providing field effect transistors having elevated sources and elevated drains, and having nitride encapsulated word lines. However, the artisan will appreciate applicability of the invention to other aspects of semiconductor processing with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents.